? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan7361, fan7362 high-side gate driver november 2009 fan7361, fan7362 rev. 1.0.8 fan7361, fan7362 high-side gate driver features ! floating channel designed for bootstrap operation to +600v ! typically 250ma/500ma sourcing/sinking current driving capability ! common-mode dv/dt noise canceling circuit ! v cc & v bs supply range from 10v to 20v ! uvlo function for v bs ! output in-phase with input signal ! 8-sop applications ! pdp scan driver ! motor control ! smps ! electronic ballast description the fan7361/fan7362, a monolithic high-side gate drive ic, can drive mosfets and igbts that operate up to +600v. fairchild?s high-voltage process and common- mode noise canceling techniques provide stable opera - tion of the high-side driver under high dv/dt noise circum - stances. an advanced level sh ift circuit offers high-side gate driver operation up to v s =-9.8v(typ.) for v bs =15v. the uvlo circuit prevents malfunction when v bs is lower than the specified thresh old voltage. output drivers typically source/sink 250ma/5 00ma, respectively, which is suitable for fluorescent lamp ballast, pdp scan driver, motor control, and so on. 8-sop ordering information note: 1. these devices passed wave so ldering test by jesd22a-111. for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html . part number package operating temperature range eco status packing method fan7361m (1) 8-sop -40c ~ 125c rohs tube fan7361mx (1) tape & reel fan7362m (1) tube fan7362mx (1) tape & reel
fan7361, fan7362 high-side gate driver ? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan7361, fan7362 rev. 1.0.8 2 typical application circuit d boot in2 c boot 15v r boot q1 r1 r2 v b in gnd ho v s nc 1 2 nc v cc 5 6 8 3 4 7 r3 r4 600v q2 in1 load fan7361 rev.04 figure 1. typical application circuit internal block diagram uvlo driver pulse generator v cc gnd in v b ho v s r r s q 6 7 8 3 4 2 noise canceller pin 1 and 5 are not connection fan7361 rev.04 figure 2. functional block diagram
fan7361, fan7362 high-side gate driver ? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan7361, fan7362 rev. 1.0.8 3 pin assignments v s v b fan7361 fan7362 v cc nc in ho nc 4 gnd 3 2 1 5 6 7 8 fan7361 rev.04 figure 3. pin configuration (top view) pin definitions 1 nc no connection 2 in logic input for high-side gate driver output 3 v cc supply voltage 4 gnd logic ground 5 nc no connection 6 v s high-voltage floating supply return 7 ho high-side driver output 8 v b high-side floating supply pin name function/ description
fan7361, fan7362 high-side gate driver ? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan7361, fan7362 rev. 1.0.8 4 absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be opera - ble above the recommended operating conditions and stressing the parts to these levels is not recommended. in addi - tion, extended exposure to stresses above the recommended operating conditions may affe ct device reliability. the absolute maximum ratings are stress ratings only. t a =25c, unless otherwise specified. v s high-side offset voltage v b -25 v b +0.3 v v b high-side floating supply voltage -0.3 625 v ho high-side floating output voltage v s -0.3 v b +0.3 v cc logic fixed supply voltage -0.3 25 v in logic input voltage -0.3 v cc +0.3 dv s /dt allowable offset voltage slew rate 50 v/ns p d (2)(3)(4) power dissipation 0.625 w ja thermal resistance, junction-to-ambient 200 c/w t j junction temperature +150 c t s storage temperature +150 c t a ambient temperature -40 +125 c notes: 2. mounted on 76.2 x 114.3 x 1.6mm pcb (fr-4 glass epoxy material). 3. refer to the following standards: jesd51-2: integral circuits thermal test method environmental conditions - natural convection jesd51-3: low effective thermal conductivity test board for leaded surface mount packages 4. do not exceed p d under any circumstances. recommended oper ating conditions the recommended operating conditions table defines the conditions for actual dev ice operation. recommended operating conditions are specified to ensure optimal performa nce to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. v b high-side floating supply voltage v s +10 v s +20 v v s high-side floating supply offset voltage 6-v cc 600 v ho high-side output voltage v s v b v in logic input voltage gnd v cc v cc logic supply voltage 10 20 symbol characteristics min. max. unit symbol parameter min. max. unit
fan7361, fan7362 high-side gate driver ? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan7361, fan7362 rev. 1.0.8 5 electrical characteristics v bias (v cc , v bs )=15.0v, t a = 25c, unless other wise specified. the v in and i in parameters are re ferenced to gnd. the v o and i o parameters are referenced to v s and are applicable to the respective output ho. v bsuv + v bs supply under-voltage positive going threshold v bs =sweep fan7361 8.2 9.2 10.2 v fan7362 7.6 8.6 9.6 v bsuv - v bs supply under-voltage negative going threshold v bs =sweep fan7361 7.4 8.6 9.2 fan7362 7.2 8.2 9.2 v bshys v bs supply under-current lockout hysteresis v bs =sweep fan7361 0.5 fan7362 0.4 i lk offset supply leakage current v b =v s =600v 10 a i qbs quiescent v bs supply current v in =0v or 5v 50 80 i qcc quiescent v cc supply current v in =0v 30 75 i pbs operating v bs supply current c l =1nf, f=10khz 420 550 v ih logic "1" input voltage fan7361 3.6 v fan7362 2.9 v il logic "0" input voltage fan7361 1.0 fan7362 0.8 v oh high level output voltage, v b -v ho no load 0.1 v ol low level output voltage, v ho no load 0.1 i in+ logic "1" input bias current v in =5v 50 90 a i in- logic "0" input bias current v in =0v 1.0 2.0 i o+ output high short circuit pulse current v ho =0v, v in =5v, pw 10s 200 250 ma i o- output low short circuit pulse current v ho =15v, v in =0v,pw 10s 400 500 v s allowable negative v s pin voltage for in signal propagation to ho -9.8 -7.0 v dynamic electrical characteristics v bias (v cc , v bs )=15.0v, v s =gnd, c l =1000pf and t a = 25c, unless otherwise specified. t on turn-on propagation delay v s =0v 120 200 ns t off turn-off propagation delay (5) v s =0v or 600v 90 180 t r turn-on rise time 70 160 t f turn-off fall time 30 100 note: 5. this parameter guaranteed by design. symbol characteristics test condition min. typ. max. unit symbol characteristics test condition min. typ. max. unit
fan7361, fan7362 high-side gate driver ? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan7361, fan7362 rev. 1.0.8 6 typical characteristics figure 4. i qcc vs. supply voltage figure 5. input bias current vs. input voltage figure 6. v bs uvlo vs. temp. figure 7. turn on/off propagation time vs. temp. figure 9. output sinking/sourcing current vs. temp. figure 8. rising/falling time vs. temp. 0 5 10 15 20 25 0 10 20 30 40 50 60 70 80 v cc =15v in=com=0v i qcc [ a] v cc [v] -40 c 25 c 125 c 02468101214 0 50 100 150 200 -40 c 25 c 125 c i in [ a] v in [v] -20 0 20 40 60 80 100 120 7.5 8.0 8.5 9.0 9.5 10.0 10.5 v bs [v] ambient temperature [c] vbsuvp1 vbsuvp2 vbsuvn1 vbsuvn2 0 20 40 60 80 100 120 0 20 40 60 80 100 120 140 160 180 200 ambient temperature [c] propagation delay time [nsec] ton toff -20 0 20 40 60 80 100 120 10 20 30 40 50 60 70 80 90 t r /t f [nsec] ambient temperature [c] tr tf -20 0 20 40 60 80 100 120 200 300 400 500 600 ambient temperature [c] output capability [ma] ioh+ ioh-
fan7361, fan7362 high-side gate driver ? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan7361, fan7362 rev. 1.0.8 7 switching time definition figure 10. switching time test circuit figure 11. input / output timing diagram hvic ho v s v b v cc =15v gnd in 10 f 10 f 0.1 f 0.1 f c l 15v fan7361 rev.03 in ho-v s 50% 50% 10% 90% 90% 10% 5v t off t f t r t on fan7361 rev.02
fan7361, fan7362 high-side gate driver ? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan7361, fan7362 rev. 1.0.8 8 physical dimensions 8 0 see detail a notes: unless otherwise specified a) this pack age conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern stan dard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge figure 12. 8-lead small outline package (sop) package drawings are provided as a service to customers considering fairchil d components. drawings may change in any manner without notice. please note the revision and/or date on the draw ing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild? s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
fan7361, fan7362 high-side gate driver ? 2005 fairchild semiconductor corporation www.fairchildsemi.com fan7361, fan7362 rev. 1.0.8 9
|
